1. Field of the Invention
This invention relates in general to circuitry for converting signals, and more specifically, to circuitry for translating low voltage CMOS (LVCMOS) logic level signals to corresponding low voltage PECL (LVPECL) logic level signals to permit the coupling of CMOS circuits to ECL circuits.
2. Description of Related Art
Emitter Coupled Logic (ECL) is a highly specialized logic family normally used in high speed data transition applications and for high speed data transmission. Complementary Metal Oxide Semiconductor (CMOS) logic is normally used for low power applications. There are many applications where CMOS and ECL could be used in conjunction, such as spacecraft telemetry and communications, test equipment interfaces, and electronic devices, where one part of the circuitry has low power dissipation as a design criteria, and the other part of the circuitry has high speed as a design criteria.
However, CMOS and ECL devices use different logic levels, making interfacing the two logic families difficult. A simple translation from CMOS to ECL logic levels is further complicated by propagation delay in the converter and lower signal fidelity in the CMOS circuitry. In order to couple a CMOS circuit to an ECL circuit, the output voltage from the CMOS circuit must be translated by some form of translation circuit to match the input voltages required by the ECL circuit, and the circuitry for performing such translation should minimize propagation delay and maintain good signal fidelity at high speed operation.
It can be seen, then, that there is a need for a conversion technique for CMOS to ECL logic levels.
It can also be seen, then, that there is a need for a conversion technique that has a high switching speed and eliminates noise problems between the CMOS and ECL logic levels.